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Posts in category tech
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Getting started with Verilog
After I got my FPGA dev board, I have several books in my virtual library (Humble Bundle etc.) and decided to start with Verilog. The book contained a few exercises which I tried to implement. After getting a feeling for the language - which took some time to be honest - my second step was to implement the CPU from Nandgame. (1)
I actually even thought about writing an assembler for the “machine” (2). But then again, I only tested the CPU and the Verilog modules in test benches so far. I haven’t loaded anything of that on my dev board, nor did I think about how I can “properly” simulate the CPU, including “loading” a program and viewing its state.
I think I need to play around with Verilator for that, which allows translating Verilog code to C++. This way, I should be able to control the CPU and also view its state. I’ll take a look at nand2tetris, which, to my knowledge, also contains a section about that topic. Its architecture is similar, though it uses a different instruction set.
Even playing Nandgame the first time - way back then - gave me a good insight on how CPUs work. Implementing one in Verilog makes things click further. Well, at least for simple architectures. I still have no idea how pipelining works, and all the details that entails, nor how multi-cycle-instructions work. That’s probably for another time.
You can view the code I wrote so far in my git repository.
(1) Tools that helped me were Icarus Verilog, Verilator and GTKwave, which are all contained on the OSS CAD Suite. That is, both linting and test benches.
(2) So I started with writing a disassembler first. I wanted to develop a nice syntax first, because I don’t like the syntax nand2tetris introduces. That’s not “proper assembler” for me. One of the special things of the architecture is that you can have multiple “destinations” for an operation, though - or none at all. To my shame, I used an LLM to get inspiration how the language could look like.